The present invention relates to manufacturing methods of semiconductor devices, and more particularly to a technique effectively applied to a manufacturing technology of a semiconductor device including a MISFET with a gate insulator having a high dielectric constant gate insulator and a metal gate electrode.
A metal insulator semiconductor field effect transistor (MISFET) can be manufactured by forming a gate insulator over a semiconductor substrate, forming gate electrodes over the gate insulator, and forming source and drain regions by ion implantation or the like. In general, a silicon oxide film is used as the gate insulator, and a polysilicon film is used as the gate electrode.
With miniaturization of MISFET elements, however, gate insulators have been recently thinned. In use of the polysilicon film for the gate electrode, the influence given by depletion of the gate electrode cannot be negligible. For this reason, a technique is proposed which uses a metal gate electrode as the gate electrode so as to suppress the phenomenon of depletion of the gate electrode.
The gate insulator has been thinned with the tendency toward the miniaturization of the MISFET element. When a thin silicon oxide film is used as the gate insulator, electrons flowing through a channel of the MISFET may tunnel a barrier formed by the silicon oxide film, which generates the so-called tunnel current flowing through the gate electrode. For this reason, another technique is proposed which uses the gate insulator made of a material having a dielectric constant higher than that of the silicon oxide film (that is, a high-dielectric constant material). The gate insulator has its physical thickness increased even with the same capacity as that of the silicon oxide film to thereby reduce the leak current.
Japanese Unexamined Patent Publication No. 2005-79311 (Patent Document 1) discloses a technique associated with etching of a High-k film.
Japanese Unexamined Patent Publication No. 2003-173998 (Patent Document 2) discloses a technique associated with cleaning of a semiconductor substrate.
Japanese Unexamined Patent Publication No. 2005-32851 (Patent Document 3) discloses a technique associated with etching of a High-k film.
[Related Art Documents]
[Patent Documents]
    [Patent Document 1]
Japanese Unexamined Patent Publication No. 2005-79311    [Patent Document 2]
Japanese Unexamined Patent Publication No. 2003-173998    [Patent Document 3]
Japanese Unexamined Patent Publication No. 2005-32851